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TMS320C5515
www.ti.com
2 Device Overview
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
2.1
Device Characteristics
Table 2-1 , provides an overview of the TMS320C5515 DSP. The tables show significant features of the
device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type
with pin count. For more detailed information on the actual device part number and maximum device
operating frequency, see Section 6.1.2 , Device and Development-Support Tool Nomenclature .
Table 2-1. Characteristics of the C5515 Processor
Peripherals
HARDWARE FEATURES
C5515
Asynchronous (8/16-bit bus width) SRAM,
I S
Not all peripheral pins are
available at the same time
(for more detail, see the
Device Configuration
section).
External Memory Interface (EMIF)
DMA
Timers
UART
SPI
I 2 C
2
USB 2.0 (Device only )
MMC/SD
LCD Bridge
ADC (Successive Approximation [SAR])
Real-Time Clock (RTC)
FFT Hardware Accelerator
General-Purpose Input/Output Port (GPIO)
Size (Bytes)
Flash (NOR, NAND),
SDRAM and Mobile SDRAM (16-bit bus width) (1)
Four DMA controllers each with four channels,
for a total of 16 channels
2 32-Bit General-Purpose (GP) Timers
1 Additional Timer Configurable as a 32-Bit GP Timer and/or a
Watchdog
1 (with RTS/CTS flow control)
1 with 4 chip selects
1 (Master/Slave)
4 (Two Channel, Full Duplex Communication)
High- and Full-Speed Device
2 MMC/SD, 256 byte read/write buffer, max 50-MHz clock for
SD cards, and signaling for DMA transfers
1 (8-bit or 16-bit asynchronous parallel bus)
1 (10-bit, 4-input, 16- μ s conversion time)
1 (Crystal Input, Separate Clock Domain and Power Supply)
1 (Supports 8 to 1024-point 16-bit real and complex FFT)
Up to 26 pins (with 1 Additional General-Purpose Output (XF)
and 4 Special-Purpose Outputs for Use With SAR)
320KB RAM, 128KB ROM
On-Chip Memory
JTAG BSDL_ID
CPU Frequency
Cycle Time
Voltage
LDOs
Organization
JTAGID Register
(Value is: 0x1B8F E02F)
MHz
ns
Core (V)
I/O (V)
DSP_LDO
ANA_LDO
USB_LDO
1.05-V Core
1.3-V Core
1.05-V Core
1.3-V Core
?
?
?
64KB On-Chip Dual-Access RAM (DARAM)
256KB On-Chip Single-Access RAM (SARAM)
128KB On-Chip Single-Access ROM (SAROM)
see Figure 5-45
60 or 75 MHz
100 or 120 MHz
16.67, 13.3 ns
10, 8.33 ns
1.05 V (60, 75 MHz)
1.3 V (100, 120 MHz)
1.8 V, 2.5 V, 2.75 V, 3.3 V
1.3 V or 1.05 V, 250 mA max current for DSP CPU (CV DD )
1.3 V, 4 mA max current for PLL (V DDA_PLL ), SAR, and power
management circuits (V DDA_ANA )
1.3 V, 25 mA max current for USB core digital (USB_V DD1P3 )
and PHY circuits (USB_V DDA1P3 )
PLL Options
BGA Package
Software Programmable Multiplier
10 x 10 mm
x4 to x4099 multiplier
196-Pin BGA (ZCH)
(1)
For more information on SDRAM devices support, see Section 5.9 , External Memory Interface (EMIF) .
Copyright ? 2010–2013, Texas Instruments Incorporated
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Device Overview
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